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Dr. Vijaypal Singh Rathor

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Dr. Vijaypal Singh Rathor

Assistant Professor

Email: vsrathor@iiitm.ac.in

Address:

A-208, Department of IT, ABV-IIITM, Gwalior, Morena Link Road, Gwalior-474015 (M.P.), India.

Personal Web Page: https://orcid.org/0000-0002-0326-3282

Dr. Vijaypal Singh Rathor

Biography

Vijaypal Singh Rathor did his M.Tech. from Maulana Azad National Institute of Technology, Bhopal, and PhD from ABV-Indian Institute of Information Technology and Management Gwalior, India, in 2014 and 2020, respectively. At present, he is working as an Assistant Professor in the Department of IT at ABV IIITM, Gwalior, India. Prior to joining IIITM Gwalior, he worked as an Assistant Professor at IIITDM, Jabalpur, India from 2021 to 2024. He has also worked as an Assistant Professor at Thapar University, Patiala, and Bennett University, Greater Noida, India. He has received grants of more than 90 lakhs from various funding agencies for four research projects. His research interests include Hardware Security, Secure System Design, Hardware Accelerators, Securing IoT and ML deisgns, and Applications of Machine/Deep learning. He has authored many research articles in international journals/conferences of repute, including IEEE Transactions.

 

Other Details

 

Number of PhD Students Graduated: Ongoing

Number of M. Tech. Graduated: 03

Number of Publications: 20 (Journals), 06 (Conferences), h-index: 8, i10 index: 07

Number of Projects: 05

Number of Keynote/Invited Talks Delivered: 08

Number of Committee Memberships: 01

Academic Qualifications

 

Degree

Year

Subject

University/Institution

PhD

2020

Information Technology

ABV-IIITM, Gwalior, (M.P.)

M. Tech.

2014

Information Security

MANIT, Bhopal, (M.P.)

B.E.

2011

Information Technology

SATI Vidisha, (M.P.)

Research Interests

 

Secure and Trustworthy System Design, Hardware Security, IoT and AI Security, Application of Machine Learning and Deep Learning. AI for Security, Hardware Accelerators.  

Selected Publications

 

  1. V. S. Rathor, Soykot Podder, and Shivam Dubey. "An ensemble learning model for hardware Trojan detection in integrated circuit design." Computers and Electrical Engineering, 123 (2025): 110090.
  2.  Deepak Mishra, Anil Kumar, V. S. Rathor, “A Novel Hybrid Approach Based on SVSR and TQWT for Crop Image Compression”, Computers and Electrical Engineering, Volume 122, 2025, 110008, ISSN 0045-7906.
  3. V. S. Rathor, M. Singh, K. S. Sahoo and S. P. Mohanty, "GateLock: Input-Dependent Key-Based Locked Gates for SAT Resistant Logic Locking," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 32, no. 2, pp. 361-371, Feb. 2024, doi: 10.1109/TVLSI.2023.3340350. ISSN: 1063-8210.
  4. Deepak Mishra, Anil Kumar, V. S. Rathor, G. K. Singh, “Hybrid Technique for Crop Image Compression using Discrete Wavelet Transform and Sparse Singular Vector Reconstruction”, Computers and Electronics in Agriculture, Volume 215, Nov, 2023, 108391, ISSN 0168-1699.
  5. V. S. Rathor, and G. K. Sharma, “A New Efficient ATPG and Online Checking Based Technique for Detecting Stealthy Trojans”, Microprocessors and Microsystems, Elsevier, Volume 101, 2023,104903, ISSN 0141-9331. ISSN No.: 1872-9436.
  6. V. S. Rathor, Deepak Singh, Mohit Sajwan and Simranjit Singh, “Multi-Objective Optimization based Test Pattern Generation Technique for Hardware Trojan Detection”, Journal of Electronic Testing: Theory and Application. 39, 371–385 (2023). June 16, 2023.  
  7. Richa. Sharma, V. S. Rathor; G.K. Sharma; Manisha Pattanaik, “A New Hardware Trojan Detection Technique Using Deep Convolutional Neural Network”, Integration: The VLSI Journal, Elsevier, Volume 79, Pages 1-11, July, 2021.
  8. V. S. Rathor, B. Garg and G. K. Sharma, “New lightweight Anti-SAT block design and obfuscation technique to thwart removal attack”, Integration: The VLSI Journal, Elsevier, Vol 75, pp. 178-188, Nov 2020.
  9. V. S. Rathor and G. K. Sharma, "A Lightweight Robust Logic Locking Technique to Thwart Sensitization and Cone-Based Attacks," in IEEE Transactions on Emerging Topics in Computing, vol. 9, no. 2, pp. 811-822, 1 April-June 2021.

V. S. Rathor, B. Garg and G. K. Sharma, "A Novel Low Complexity Logic Encryption Technique for Design-for-Trust," in IEEE Transactions on Emerging Topics in Computing, vol. 8, no. 3, pp. 688-699, 1 July-Sept. 2020.

Research Lab(s)

 

Wireless Sensor Networks (WSN) Lab

Competitive Grant(s)

 

Sl

Grant (Project/ Consultancy)

Funding Agency

PI/Co-PI

1

Vulnerability Analysis of IoT Devices Against Side Channel Analysis and Mitigation

FIG

PI

2

A Lightweight Hardware Logic Locking based Data Encryption Model for Securing IoT Devices from Hardware and Cyber Attacks

DSCI

PI

3

Techniques and Toolkit for Analysis of Multifactor Authentication

DRDO

Co-PI

4

UAV-assisted Wi-Fi Geofencing for UAV Tracking and Activity Monitoring in Restricted Perimeter

TiHAN, IIT Hyderabad

Co-PI

5

 HT-Pred: A complete defensive machine learning tool for Hardware Trojan Detection.

DSCI

PI

Faculty Development / Management Development / Workshops / Conference

 

SN

Title

Period

Sponsoring Organization

Venue

From

To

1.

Machine Learning for Social Goods Workshop

April 2, 2025

April 9, 2025

EICT, Academy IIITDM Jabalpur

Online

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